1. Field of the Invention
The present invention relates to a dual damascene process and, more particularly, to a dual damascene process for increasing the adhesion between the inter-level dielectric and a metal barrier layer in which an in-situ oxide liner is used for a dielectric barrier layer.
2. Description of the Related Art
In semiconductor processing, multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below 0.25 m design rules. One example of an advanced interconnect architecture is a dual damascene structure. The dual damascene process offers advantages in process simplification, lithography and critical dimension control. In addition, because of the simplicity of the dual damascene process, materials of the conductive layer/inter-level dielectric (ILD) using an existing aluminum/silicon oxide scheme can be cost-effectively replaced by the use of a copper/low-dielectric constant (low-k) material scheme.
One drawback of using copper is that copper diffuses/drifts easily into adjoining low-k ILD, and it causes damage to neighboring devices on the semiconductor substrate. Furthermore, copper may reach the silicon substrate and then degrade the performance of device. To solve this problem, a metal barrier layer made of Ta/TaN, Ti/TiN or W/WN layer is provided to encapsulate copper from the surrounding ILD. The metal barrier layer can prevent possible interaction between the copper interconnect and the low-k ILD, and also provide adhesion therebetween.
FIGS. 1A to 1C depict a dual damascene process using a metal barrier layer according to the prior art. Referring to FIG. 1A, on a semiconductor substrate 10, a dual damascene opening 25 comprises a via hole 23 that exposes a predetermined region of a conductive wire 12 and is surrounded by a first low-k ILD 16, and a trench 24 that is over the via hole 23 and surrounded by a second low-k ILD 20. A dielectric separation layer 14 is covered on the semiconductor substrate 10 to expose the predetermined region of the conductive wire 12, an etch stop layer 18 is deposited on the first low-k ILD 16, and a hard mask 22 is patterned on the second low-k ILD 20. Referring to FIG. 1B, a metal barrier layer 26 is deposited on the exposed surface of the semiconductor substrate 10 so as to cover the sidewall of the dual damascene opening 25. Then, a conductive layer 28 made of copper is deposited to fill the dual damascene opening 25. Next, a chemical-mechanical polishing (CMP) process is used to polish away the excess conductive layer 28 above the trench 24 in which the hard mask 22 serves as a polish-stop layer. Thus, as shown in FIG. 1C, the remaining part of the conductive layer 28 serves as the dual damascene structure.
However, another shortcoming associated with the dual damascene structure is the outgassing phenomenon. Outgassing is a critical issue from the first low-k ILD 16 and the second low-k ILD 20 to the metal barrier layer 26. It damages adhesion between the low-k ILD 16, 20 and the metal barrier layer 26, and negatively impacts the thermal reliability/hardness of the dual damascene structure. Thus, a dual damascene process using a dielectric barrier layer between the low-k ILD and the metal barrier layer solving the aforementioned problems is desired.
It is a principle object of the invention to provide means for increasing the adhesion of the low-k dielectric layer and the metal barrier layer.
It is another object of the invention to prevent outgas effect from the low-k dielectric layer.
Yet another object of the invention is to provide a dual damascene structure with better thermal stability.
It is a further object of the invention to provide a dual damascene structure with better hardness.
Still another object of the invention is to reduce the cost of fabrication of a dual damascene process.
Accordingly, the present invention is a dual damascene process using an in-situ oxide liner for a dielectric barrier layer. In a dual damascene opening, the oxide liner formed on the sidewall of a low-k dielectric layer is sandwiched between the low-k dielectric layer and a metal barrier layer, thus solving the aforementioned problems.
In the dual damascene process, a semiconductor substrate is provided with at least a dual damascene opening having a via hole exposing a predetermined region of a metal wire and surrounded by a first low-k dielectric layer, and a trench over the via hole surrounded by a second low-k dielectric layer. The materials of the first low-k dielectric layer and/or the second low-k dielectric layer may be selected from spin-on polymer (SOP), such as FLARE, SILK, Parylene, PAE-II andpolyimide, and formed through a spin-coating process. Alternatively, the materials of the first low-k dielectric layer and/or the second low-k dielectric layer may be selected from black diamond, Coral, Aurora, Green Dot or other low-k dielectric materials, and formed by a CVD process. It is appreciated that how the dual damascene opening is fabricated is a design choice dependent on the fabrication process being employed.
When a photoresist layer for patterning the dual damascene opening is stripped, an oxidation process is performed prior to a wet cleaning process, thus an in-situ oxide liner is formed on a sidewall of the first low-k dielectric layer and the second low-k dielectric layer to serve as a dielectric barrier layer for improving the adhesion between the low-k ILD and a metal barrier layer. A metal reduction step is then required so as to strip the in-situ oxide liner on the exposed regions of the metal wire. Also, a degas step is needed to remove outgas from the first low-k dielectric layer and the second low-k dielectric layer.
A metal barrier layer, preferably made of Ta/TaN, Ti/TiN or W/WN, is then conformally deposited along the exposed surface of the semiconductor substrate to encapsulate copper interconnect from the surrounding low-k dielectric layer and to provide the adhesion between the copper interconnect and the low-k dielectric layer. Next, a conductive layer made of copper is deposited by, for example, PVD, CVD, electro-plating technique, or a combination of these techniques to fill the dual damascene opening. The conductive layer and the metal barrier layer residing above the trench level are removed, preferably by chemical-mechanical polishing (CMP). The remaining part of the conductive layer serves as the dual damascene structure.
Finally, a sealing layer, preferably made of SiN or SiC, is deposited over the exposed surface of the semiconductor substrate to cover the top of the dual damascene structure. This prevents the dual damascene structure from oxidizing and prevents the atoms/ions in the dual damascene structure from diffusing into a subsequently formed dielectric layer over the dual damascene structure. In addition, by repeating the processes, additional interconnect structures can be fabricated to form metallization levels above the dual damascene structure.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.